The present invention relates to encapsulation of microelectronic assemblies.
As described, for example, in U.S. Pat. No. 5,659,652; in U.S. patent application Ser. No. 08/532,235 filed Sep. 22, 1995; and in U.S. patent application Ser. No. 08/726,697, the disclosures of which are hereby incorporated by reference herein, microelectronic assemblies can be made with microelectronic elements such as a semiconductor chip having contact thereon and a flexible, sheet-like dielectric element having terminals thereon electrically connected to the contacts of the chip. The flexible dielectric element forms a top surface of the assembly, whereas the surface of the chip facing away from the flexible dielectric element forms the bottom surface of the assembly. For example, where the dielectric sheet overlies the front or contact-bearing surface of the chip, the back surface of the chip forms the bottom surface of the assembly. The assembly may also include a compliant layer such as an elastomer or gel disposed between the dielectric sheet and the chip to provide mechanical decoupling of the sheet and terminals from the chip.
As disclosed in the aforementioned patents and patent applications, such compliant layers can be made by providing a porous layer such as plurality compliant pads between the chip and the sheet, electrically connecting the terminals to the contacts of the chip and then encapsulating the resulting assembly with a curable liquid encapsulant so that the encapsulant penetrates into the porous layer and also covers the connections at the contacts on the chip. Upon curing of the encapsulant to form a compliant material, the encapsulant in the porous layer forms part of the compliant layer. In making assemblies of this nature, it is desirable to avoid applying encapsulant onto the top and bottom surfaces of the assembly. That is, it is desirable to avoid applying an encapsulant on the top surface of the dielectric sheet and on the terminals or on the surface of the chip defining the back surface of the assembly. It is also desirable to ensure that the encapsulant completely fills the porous layer, to provide a substantially void-free compliant layer in the final assembly.
Several useful methods of applying and curing the encapsulant in microelectronic assemblies have been proposed in commonly assigned, copending United States patents applications and patents. For example, as set forth in the aforementioned Ser. No. 08/532,235 application, the dielectric sheets incorporated in the assemblies typically include apertures or "bond windows" which provide access to the contacts of the chip during the step of electrically connecting the terminals to the chip. After these connections have been made, a top cover layer may be applied over the top surface of the dielectric sheet. Typically, several assemblies are provided in a side by side arrangement so the same top cover layer lies on the top surfaces of several assemblies. The top cover layer seals the bond windows and also seals spaces between the dielectric sheets of adjacent assemblies. A bottom cover layer is provided over the bottom surfaces of the assemblies. The cover layers and assemblies are held in a fixture. A pocket in the fixture holds a curable liquid encapsulant. After the space between the cover layers is brought to subatmospheric pressure by connecting the fixture to a vacuum source, the fixture is tilted so as to pour the liquid encapsulant into the space between the cover layers whereupon the encapsulant is cured while the components remain in place in the fixture. The top and bottom cover layers retain the encapsulant and prevent it from contaminating the bottom surfaces of the chips or the top surfaces of the dielectric layers.
As described in the aforementioned U.S. Pat. No. 5,659,952 and U.S. patent application Ser. No. 08/726,697 the encapsulant may be applied using a nozzle or a syringe around the periphery of each subassembly. For example, as shown in the '697 application, a plurality of assemblies can be made using a single, unitary dielectric sheet element, commonly referred to as a "tape" which incorporates the dielectric sheets of several subassemblies. The chips may be attached to the tape and electrically connected to the terminals of the tape. At this point, a needle connected to an encapsulant dispenser is used to trace a pattern around the peripheries of the individual chips, so that the encapsulant flows into the space between each chip and the dielectric layer. A covering layer may be used to close the bond windows in the tape during this process. Also, during this process, the tape typically is held in a frame. In a further variant of this process, described in U.S. patent application Ser. No. 08/975,590, the disclosure of which is also incorporated by reference herein, the frame and tape are placed in a vacuum chamber, and the encapsulant dispensing operation is conducted inside the chamber, while the assembly is under vacuum. When the vacuum is released, and the chamber is brought to atmospheric or superatmospheric pressure, the pressure forces the encapsulant into the porous layer between the chip and the tape. Further, as described in U.S. patent application Ser. No. 09/012,590, filed Jan. 23, 1998, the disclosure of which is also incorporated by reference herein, it is convenient to use a frame to hold the tape during the assembly procedures. For example, the compliant pads used to form the porous layer may be applied to the tape while the tape is mounted on the frame and the chips may be mechanically attached to the pads and electrically connected to the terminals also while the tape is mounted on the frame.
Despite all of these advances in manufacture of microelectronic assemblies, still further improvement would be desirable.